VLSI Design Services and Custom IP Solutions

ASIC Design Services specializing in physical design and verification offer Custom IP Solutions and support in VLSI Design.

VLSI Design Services and Custom IP Solutions

ASIC Design Services specializing in physical design and verification offer Custom IP Solutions and support in VLSI Design.

Overview

25+ years of experience in IC physical design/implementation

VLSI

MMMC , MSMV design implementation
Vertical Implementation solutions : Floorplanning, clock tree synthesis (CTS), place and route (PNR), and signoff. We also provide UPF/CPF development support and validation
VLSI flow deployment at customer sites (RTL to GDSII)
Custom IP integration solutions: Integration of JunexIC IPs and other vendor IPs.

DFT insertion (Scan, MBIST,BSCAN, SCAN), DFT verification

Using Cadence Modus or Siemens Tessent , Stuck-At and At-speed scan insertion, Scan Compression, Mbist, Boundary Scan, OCC insertion

Timing Constraint (SDC) development support for large SOCs

Supporting > 100 analysis views for deep submicron production tapeouts
Foundry recommended derates applied
Report aggregation
ECO generation from Tempus

Hardware AI Models: IP design and implementation

AI related custom hardware IPs
AI transformer model building blocks parameterized for performance / area tradeoff: RMS norm, SwigLU, RoPE, QKVO projection computations, KV Cache computations (attention scores) , FFN computations etc.
Hardware ROM based vector embedding
Model hardening (frozen model): Mapping existing "forzen" AI models (transformer based LLMs or ML or VLM models) to silicon including storing model parameters on silicon to largely eliminate need for HBMs
Note: currently decode only models are supported.

Frozen / Hardcoded AI Model Implementation

As AI models mature the possibility of having hardcoded (frozen) models becomes more attractive
We offer full chip AI design services (rtl to tapeout) with ICs targetting the implementation of specific models (example chip: llama2 110M model). Models larger than ~100-200M parameters would be implemented as multiple asics.

Serial Communication IP design and implementation

SPI / I2C design and implementation offering Custom IP Solutions from specification to GDS. Our silicon-proven designs focus on mixed signal RF products, supporting mixed signal nodes like GF 9HP SiGe, GF 45 SPCLO, and TSMC 12FFC, GF22FDXPLUS, we specialize in Custom IP development and silicon implementation under NDA (from Spec to GDS) for variety of markets while emphasizing low power solutions for specific markets such as IoT.

VLSI

Close-up of a microchip on a circuit board with intricate copper pathways.

IC Physical Design Services: Synthesis/Place and Route / Physical verification / Conformal LEC

RTL to GDS implementation including Synthesis, PNR, STA, LEC,CLP
Final physical signoff using Siemens Calibre or Cadence Pegasus
IR /EM analysis

Process Nodes Supported

TSMC (3 way NDA required)
- CLN22ULL
- CRN28HPCPLUS
- TSMC N7/N5
GF (3 way NDA required)
- F22FDXPLUS
- GF/IBM 7HP/9HPSiGe
- 45SPCLO

IC Chip Implementation

Top level Floorplanning, Power grid planning (multi-domain , island). Padring PG hookup
Physical integration of analog IPs in digital on top SOCs (RF , ADC , power management units).
Hierarchical SOC physical development using Liberty / LEF / ILM models
Bump assignment and routing co-designed with package
Wire bond padring design to meet QFN and other wire bond packaging requirements
Package design support (flip chip or wirebond)
Timing closure (prects, cts, postroute) : path grouping and physical fencing / regioning etc for improved timing convergence and hotspot control

Custom IP implementation for mixed-signal devices, Serial IP (SPI,I2C) Spec to GDS implementation

Implementation of customer register map access via SPI/I2C
RTL to GDS

DFT

MBIST insertion with BISR if required.
BSCAN insertion
At-Speed scan insertion with OCC insertion
Stuck-At scan insertion
Compression
Tessent IJTAG , ICL PDL
TDR insertion for PLL and PMU (power management unit), RF control in test mode

IR Analysis

Power / IR Analysis: Static, Dynamic (vector based) , EM analysis (power and signal)

Liberty model generation for IPs from characterization data

Work with Analog / RF teams for building lef and liberty models for digital SOC integration

VLSI Design Services and Custom IP Solutions

VLSI Design Services and Custom IP Solutions

Our Services

Overview

VLSI Capabilities

VLSI Capabilities

VLSI Capabilities

VLSI Capabilities

VLSI Capabilities

Design Verification

Design Verification

Design Verification

Toolsets

Design Verification

Design Verification

About JunexIC Company

Our Vision

Overview

25+ years of experience in IC physical design/implementation

VLSI

DFT insertion (Scan, MBIST,BSCAN, SCAN), DFT verification

Timing Constraint (SDC) development support for large SOCs

Hardware AI Models: IP design and implementation

Frozen / Hardcoded AI Model Implementation

Serial Communication IP design and implementation

VLSI

IC Physical Design Services: Synthesis/Place and Route / Physical verification / Conformal LEC

Process Nodes Supported

IC Chip Implementation

Custom IP implementation for mixed-signal devices, Serial IP (SPI,I2C) Spec to GDS implementation

DFT

IR Analysis

Liberty model generation for IPs from characterization data

Design Verification

RTL and Gate verification of JunexIC designed Custom IPs

DFT RTL and Gate Level Verification

Toolsets

Cadence Implementation Tools

Cadence Conformal LEC/CLP

Cadence Pegasus Physical Verification Tools

Siemens Tessent/Calibre

Contact Us

Drop us a line!

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